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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 3-6. LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing
PDINHIBR3
EBSR PPMODE BITS
REGISTER
BIT
FIELDS (1)
P2PD
P3PD
P4PD
P5PD
P6PD
P7PD
P8PD
P9PD
P10PD
P11PD
P12PD
P13PD
P14PD
P15PD
PIN NAME
LCD_EN_RDB/SPI_CLK
LCD_D[0]/SPI_RX
LCD_D[1]/SPI_TX
LCD_D[2]/GP[12]
LCD_D[3]/GP[13]
LCD_D[4]/GP[14]
LCD_D[5]/GP[15]
LCD_D[6]/GP[16]
LCD_D[7]/GP[17]
LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK
LCD_D[9]/I2S2_FS/GP[19]/SPI_CS0
LCD_D[10]/I2S2_RX/GP[20]/SPI_RX
LCD_D[11]/I2S2_DX/GP[27]/SPI_TX
LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK
LCD_D[13]/UART_CTS/GP[29]/I2S3_FS
LCD_D[14]/UART_RXD/GP[30]/I2S3_RX
LCD_D[15]/UART_TXD/GP[31]/I2S3_DX
LCD_CS0_E0/SPI_CS0
LCD_CS1_E1/SPI_CS1
LCD_RW_WRB/SPI_CS2
LCD_RS/SPI_CS3
MODE 0
000
(Reset Default)
LCD_EN_RDB
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
LCD_D[8]
LCD_D[9]
LCD_D[10]
LCD_D[11]
LCD_D[12]
LCD_D[13]
LCD_D[14]
LCD_D[15]
LCD_CS0_E0
LCD_CS1_E1
LCD_RW_WRB
LCD_RS
MODE 1
001
SPI_CLK
SPI_RX
SPI_TX
GP[12]
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
MODE 2
010
LCD_EN_RDB
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
GP[18]
GP[19]
GP[20]
GP[27]
GP[28]
GP[29]
GP[30]
GP[31]
LCD_CS0_E0
LCD_CS1_E1
LCD_RW_WRB
LCD_RS
MODE 3
011
LCD_EN_RDB
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
SPI_CLK
SPI_CS0
SPI_RX
SPI_TX
I2S3_CLK
I2S3_FS
I2S3_RX
I2S3_DX
LCD_CS0_E0
LCD_CS1_E1
LCD_RW_WRB
LCD_RS
MODE 4
100
LCD_EN_RDB
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
LCD_CS0_E0
LCD_CS1_E1
LCD_RW_WRB
LCD_RS
MODE 5
101
LCD_EN_RDB
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
SPI_CLK
SPI_CS0
SPI_RX
SPI_TX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
LCD_CS0_E0
LCD_CS1_E1
LCD_RW_WRB
LCD_RS
MODE 6
110
SPI_CLK
SPI_RX
SPI_TX
GP[12]
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
I2S3_CLK
I2S3_FS
I2S3_RX
I2S3_DX
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
(1)
The pin names with PDINHIBR3 register bit field references can have the pulldown resistor enabled or disabled via this register.
62
Device Configuration
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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